(China (Mainland))
Product Summary
The EPF10K200SRC240-1 is a FLEX 10K device. Based on reconfigurable CMOS SRAM elements, the FLEX architecture incorporates all features necessary to implement common gate array megafunctions. With up to 200,000 typical gates, the EPF10K200SRC240-1 provides the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device.
Parametrics
EPF10K200SRC240-1 absolute maximum ratings: (1)VCCINT, Supply voltage With respect to ground: –0.2 to 4.6 V; (2)VI, DC input voltage: –0.5 to 3.6 V; (3)IOUT, DC output current, per pin: –25 to 25 mA; (4)TSTG, Storage temperature No bias: –65 to 150℃; (5)TAMB, Ambient temperature Under bias: –65 to 135℃; (6)TJ, Junction temperature: 135℃.
Features
EPF10K200SRC240-1 features: (1)Embedded programmable logic devices (PLDs), providing system-on-a-programmable-chip (SOPC) integration in a single device; (2)Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions; (3)Dual-port capability with up to 16-bit width per embedded array block (EAB); (4)Logic array for general logic functions; (5)High density; (6)30,000 to 200,000 typical gates (see Tables 1 and 2); (7)Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be used without reducing logic capacity; (8)System-level features; (9)MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices; (10)Low power consumption; (11)Bidirectional I/O performance (tSU and tCO) up to 212 MHz; (12)Fully compliant with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz; (13)1 speed grade devices are compliant with PCI Local Bus Specification, Revision 2.2, for 5.0-V operation; (16)Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic.
Diagrams
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 EPF10K200SRC240-1X |
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IC FLEX 10KS FPGA 200K 240-RQFP |
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