SAA7111AHZ

Product Summary

The Enhanced Video Input Processor (EVIP) SAA7111AHZ is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multi-standard decoder (PAL BGHI, PAL M, PAL N, NTSC M, NTSC-Japan NTSC N and SECAM), a brightness/contrast/saturation control circuit, a colour space matrix and a 27 MHz VBI-data bypass. The pure 3.3 V CMOS circuit SAA7111AHZ, analog front-end and digital video decoder, is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into CCIR-601 compatible colour component values. The SAA7111AHZ accepts as analog inputs CVBS or S-video (Y/C) from TV or VTR sources. The circuit is I2C-bus controlled. The SAA7111AHZ then supports several text features as Line 21 data slicing and a high-speed VBI data bypass for Intercast.

Parametrics

SAA7111AHZ absolute maximum ratings: (1)VDDD, digital supply voltage: -0.5 to +4.6 V; (2)VDDA, analog supply voltage: -0.5 to +4.6 V; (3)Vi(A), input voltage at analog inputs: -0.5 to VDDA + 0.5(4.6 max.)V; (4)Vo(A), output voltage at analog output: -0.5 to VDDA + 0.5 V; (5)Vi(D), input voltage at digital inputs and outputs, outputs in 3-state: -0.5 to +5.5 V; (6)Vo(D), output voltage at digital outputs, outputs active: -0.5 to VDDD + 0.5 V; (7)△VSS, voltage difference between VSSAall and VSSall: -100mV; (8)Tstg, storage temperature: -65 to +150℃; (9)Tamb, operating ambient temperature: 0 to 70℃; (10)Tamb(bias), operating ambient temperature under bias: -10 to +80℃; (11)Vesd, electrostatic discharge all pins: -2000 to +2000 V.

Features

SAA7111AHZ features: (1)Four analog inputs, internal analog source selectors, e.g. 4× CVBS or 2× Y/C or (1 × Y/C and 2 × CVBS); (2)Two analog preprocessing channels; (3)Fully programmable static gain for the main channels or automatic gain control for the selected CVBS or Y/C channel; (4)Switchable white peak control; (5)Two built-in analog anti-aliasing filters; (6)Two 8-bit video CMOS analog-to-digital converters; (7)On-chip clock generator; (8)Line-locked system clock frequencies; (9)Digital PLL for horizontal-sync processing and clock generation; (10)Requires only one crystal (24.576 MHz) for all standards; (11)Horizontal and vertical sync detection; (12)Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC standards; (13)Luminance and chrominance signal processing for PAL BGHI, PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43, NTSC-Japan and SECAM; (14)User programmable luminance peaking or aperture correction; (15)Cross-colour reduction for NTSC by chrominance comb filtering; (16)PAL delay line for correcting PAL phase errors; (17)Real time status information output (RTCO); (18)Brightness Contrast Saturation (BCS) control on-chip; (19)720 active samples per line on the YUV bus; (20)Low power (<0.5 W), low voltage (3.3 V), small package (LQFP64); (21)5 V tolerant digital I/O ports.

Diagrams